Akash Singh 阿卡什

Enthusiastic Master Student and experienced Software Developer with demonstrated working history for more than 1-year in IT and Service Industry.

Working on Algorithm Design , Scan Chain Diagnosis using ML, Fail Analysis in Semiconductors,  Defect detection and reduction, Multi-objective optimization, Reinforcement Learning, Deep Learning, Evolutionary Algorithms.

Strong technical skills, including Digital IC design, APR tools, pre-simulation and post-simulation analysis, RAM Testing , Fault repair using BISR, DFT Process flow, Redundant Analysis and CMOS technology . 

Also familiar with Semiconductor fabrication flow, electronics fundamentals, DSP, IC test algorithms and test bench development, Interconnects, 

NTHU EE, Hsinchu, TW
[email protected]

Work Experience

Multi Objective Control Lab MOC, NTHU ,Research Assistant, May 2019 ~ Present

  • Working on AI algorithm design and Implementation to solve multi-objective problems.
  • Involve with performing  simulation for modular robots in robust environment to learn faster by energy-efficient way.
  • Exploring multiple control AI techniques such as Reinforcement learning (Q-learning, SARSA, policy gradient) , Deep RL (Deep Q, Actor-Critic, DDPG, PPO) and Evolutionary Algorithms (Genetic Algorithm, NEAT).

IC design and Exploration Lab IC-Dex, NTHU ,Research Assistant, March 2018~ Apr 2019

  • Co-worked with lab members on industry sponsored project  to develop a tool that can perform Scan Chain Diagnosis of  IC using Multi stage ANN for different fault types such as Stuck-at fault, stuck-open fault.
  • Performed simulation of optimizing IC test process by different Deep Learning models such as CGNN, CNN, RNN, LSTM using tensorflow, keras and TFLearn library and python.
  • Coordinated with Scientist and Engineers of Mentor Graphics, USA team to develop and train efficient Machine learning models and pre-model data preparation.
  • Worked on IC design, synthesis and Layout  tools like Cadence Virtuoso, Laker, Composer, Design Compiler and  Verilog, Hspice, C++ programming. 

Mentor Graphics Hsinchu,TW, Summer Research Intern, March 2017 ~ March 2018

  • Worked closely with DFT team to understand the Build in self-test (BIST) flow, Commercial tool tessent Faul finding techniques for Intermittent and Permanent faults in IC.
  • Cooperated with US-based DFT team for enhancing commercial test tool to incorporate ML for advance IC testing and diagnosis.
  • Supported in Data preparation and Data refinement for designed Neural Network models to be tested by considering different Benchmark and Industry based circuit.

TATA Consultancy Services, Bangalore, India, Assistance System Engineer,  May 2019 ~ Present

  • Worked as ABAP Software developer to design enterprise software for managing business operations and customer relations.
  • Actively participated in core development  for different client by using SAP platforms such as Webdynpro, SAP HANA database.
  • Learn about team coordination and professional client meeting to demonstrate projects and process flow. 


Preference Based Weighted Sum Multi-Objective Energy Efficient Gait Optimization for Snake-like Modular Robot, MOC Lab, June 2018 - Current

  • Simulation on Modular robot reconfiguration and Control  for adopting snake like shape. 
  • Multi-objective optimization of gait parameters using weighted sum approach for energy efficient locomotion.
  • Using python, C++ programming, Tensor flow framework and VREP physics engine to perform simulation

Diagnosis of Intermittent Scan Chain Faults Through a Multi-Stage Neural Network Reasoning Process, IC-DeX Lab, June 2018 - Apr 2019

  • Co-worked with Lab mates to design tool for IC testing using Deep Learning.
  • Worked on NN model fine tuning and parameter setup to get higher test and validation accuracy.
  • Analyse different net-list to extract the test information for data preparation.
  • Extracted Integer failure log and Combined failure logs from log file generated from commercial scan chain test tool.

Implementation of A Multi-Modulus Frequency Divider, Course Project, VLSI Design NTHU ,Oct 2019 - Dec - 2019

  • Implemented multi-modulus frequency divider with total 4 modes operation (÷16 / 18/ 20 / 22). 
  • Circuit synthesis done by Composer tool as well Hspice and Layout design on Laker tool. 
  • Pre-simulation and Post -simulation done to get minimum area and power consumption by selecting TSPC DFF.
  • Achieved maximum operating frequency 8 GHz pre-sim and 5 GHz post sim.

RL based Control algorithm design for classical Control System, Course Project, System Theory-RL, NTHU,Oct 2019 - Dec - 2019

  • Solving gym environment classic control problem by implementing multiple reinforcement learning methods such as Q-Learning, Deep Q learning, Actor-Critic, Deep Deterministic Policy Gradient(DDPG), Proximal policy Optimisation(PPO).

Implementation of BIST circuit for MOVI Alogorithm for SRAM Testing, Course Project, Semiconductor Memory testing,  NTHU Feb 2018 - May 2019

  • MOVI Algorithm is known for Memory-Testing. Its March-based test elements are all simple and possess good fault coverage (AF,SAF,TF and CF). 
  • Designed a BIST circuit and its controller for SRAM Testing using MOVI Algorithm.

Other Projects

  • Visual Question answering - VQA : final project of Computer vision course 
  • Music Composition using LSTM Network : final project of Computer vision course

Honors & Awards 

2013 Finalist, International student Project Contest Srajan15 held by MANIT and IEEE Bhopal India 

2013 Finalist, National level Exhibition I-FAST SAVISHKAR15 organized by MANIT,M.P and C.G. Council of Science and Technology Bhopal India 

2014 Finalist, Free Scale Cup competition (TFC-2015) organised by Freescale and Mathswork and held at IIS-Banglore  India 

2013, 14 Selected 2 times , E-yantra competition held by IIT- bombay and MHRD Delhi India


National Tsing Hua University, MASTERS IN ELECTRICAL ENGINEERING DEPARTMENT, 2018 ~ 2020

Shri Mata Vaishno Devi University, BACHELOR OF TECHNOLOGY, 2012 ~ 2016

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