王韶逸

Senior process engineer  •  Taiwan Semiconductor Manufacturing Company (TSMC)

十一月 2009 - 三月 2021

• 2009-2012:  200mm Etch process engineer(Fab5)，FOEL process(STI，Poly layer process)，Wet  branch(Caros、H3PO4、APM clean)。
• 2012-2015: 200mm Etch process central team Fab, Fab3/5/6/8)，Senior Engineer，major for process improve、new recipe develop、cross fab CIP fan out、cost benefit(2nd source、parts change evaluate)。1. Recipe tuning: SPA etching endpoint mode developing、ASH WPH recipe、dummy step time reducing、profile healthy improve; 2.Cost reduction: Gas/chemical and 2nd source evaluate, like as ESC、green chiller、wafer raw material…etc。
• 2015-2019:  200mm Etch process engineer(Fab5)，section leader of BOEL process，contact layer，recipe turning、KPI improve(SPC、Hold time、scrap、customer/internal Audit)、high/low light reporting。lead 6 engineers of section and 8 assist-engineers of department for daily handover、job dispatch、CIT schedule 。
• 2019-2021:  300mm Etch process engineer(Fab12A)，BEOL  process，Inter-via/top-via  process，SPC review & KPI improve。