1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc.

2. Build testbench, develop and maintain in-house VIP

3. Create rand constraint conditions, analysis coverage holes and fill them

4. Create function coverage points to make sure all functions are under test

1. Familiar with Verilog, SystemVerilog

2. Exposure to UVM methodology

3. Familiar with AMBA AXI/ACE/CHI/AHB/APB protocol and peripheral IP

Protocol

4. Familiar with C++/OOP