[Responsibilities]
1、Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing
2、STA timing analysis and fixing
3、Physical verification, including DRC, LVS, IR drop and DFM analysis.
4、Physical design flow development and automation

[Qualifications]
1、Minimum Qualifications:
　- 電機、資訊相關科系，學士或碩士畢業
　- 具有獨立思考的能力，並習慣與團隊合作解決問題
　- 高度的學習動機、願意投入精力分析和解決問題
2、Preferred Qualifications:
　- 具有IC相關 tape out經驗
　- 熟悉Tcl, Python語言