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Logo of CakeResume Headhunting Recruitment Service.
Logo of CakeResume Headhunting Recruitment Service.
CakeResume Headhunting Recruitment Service
Logo of CakeResume Headhunting Recruitment Service.
CakeResume Headhunting Recruitment Service
Logo of CakeResume Headhunting Recruitment Service.
CakeResume Headhunting Recruitment Service
Jobs
The employer was active about 17 hours ago
• 面板驅動IC 或 SoC 設計
300台灣新竹市東區
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
台灣新竹市新竹
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Hsinchu, Hsinchu City, Taiwan
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Verify digital designs of large SoCs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology...
Verify digital designs of large SoCs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology...
Zhudong Township, Hsinchu County, Taiwan 310
2M ~ 3M TWD / year
2 years of experience required
No management responsibility
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
Taipei, Taiwan
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
碩士以上;電機、電機與控制、電信、電子相關科系畢業為主 需具備5年以上相關工作經驗 熟悉C、Verilog及一般IC設計流程,有數位 IC設計經驗或FPGA使用經驗,或通訊網路電路設計開發經驗者為佳 具數位電路後段整合經驗者尤佳
碩士以上;電機、電機與控制、電信、電子相關科系畢業為主 需具備5年以上相關工作經驗 熟悉C、Verilog及一般IC設計流程,有數位 IC設計經驗或FPGA使用經驗,或通訊網路電路設計開發經驗者為佳 具數位電路後段整合經驗者尤佳
Hsinchu, Hsinchu City, Taiwan
2M ~ 3M TWD / year
5 years of experience required
No management responsibility