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Hot🔥 – The world's leading terminal edge AI solution manufacture- Design Verification Engineer - DC
Job Description
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
2.Create verification environments using SystemVerilog, SystemC or UVM.
3.Identify and write all types of coverage measures for stimulus and corner-cases.
4.Debug tests with design engineers to deliver functionally correct design blocks.
5. Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements
1.Experience in verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog or SystemC for ASICs and/or SoCs.
2. Experience with the creation of and usage of verification components and environments in a standard verification methodology such as UVM, OVM, or VMM.
About us
🔥This is the CakeResume Headhunting Recruitment Service official web page🔥
Connecting Companies with Top Tech Talent. CakeResume’s Recruitment Consulting Team has successfully helped Fortune 500 & startup companies recruit top talent of all kinds.
- Millions of huge talent database – CakeResume + LinkedIn + Direct Sourcing.
- Faster sourcing and matching with CakeResume AI.
- Dedicated Recruitment Consultant team. Will help you find the right talent and improve your recruiting process.
- https://www.cakeresume.com/recruitment-service?ref=navs_recruitment_service
About CakeResume:
CakeResume is the Leading Asia talent platform. Now we have over 3,000,000+ active resumes in our database and still it is increasing every day.
Currently more than 5,000 clients, ranging from Software like Appier、Line、Crypto.com、Trend Micro、17Live to large companies like Amazon、Google、MediaTek、 Realtek、TSMC、Micron etc. are using our recruitment services.
Team
