SUMMARY

Take the major responsibility for Signal integrity design for Server and Storage. Provide necessary inputs regarding high-speed signal quality and design constraints to electronics designers for signal & design quality assurance. Drive innovation and continuous improvement within Jabil Circuit by harnessing new technologies and methodologies. Provide exceptional support to external and internal customers, team members, and other persons through technical project coordination.

ESSENTIAL DUTIES AND RESPONSIBILITIES include, but are not limited to the following:

• Principle point of contact to internal or external team, partners and customer
• SI simulation resource (Tools/Human) management
• SI design schedule/Status/Risk/Issue management
• Create SI check list and review or generate SI reports
• Publish final SI reports
• SI team defect quality and lesson learnt
• SI engineer training
• Responsible for the high-speed signal pre-simulation and post-simulation, layout constraints preparation, and PCB design
• Perform system level’s signal integrity and timing analysis on boards, packages, connectors and ASICs etc.
• Cooperate with EA (Electronic Analysis) engineers to develop EA Test plans and basic bring-up/functionality testing plans
• Correlate SI simulations and EA tests to validate the modeling methodology
• Contribute to the design trade-offs and evaluation of mechanical, electrical, and thermal performance of both components level and system level
• Cooperate with electronics engineers for signal issues & Lab debug

REQUIREMENTS:

• Master’s degree in electrical engineering or equivalent with at least 5 years related experience in PC/Server/Storage signal simulation
• Proficient with board level’s reflection, crosstalk, ground bounce, bypassing techniques for power/ground noise reduction, termination techniques for reflection noise control
• Proficient with on chip SI including core noise modeling, on chip crosstalk, I/O selection, chip pin-out assignment, package selection and pin-out arrangement
• Proficient with PCB cross-section/stackup design and trade-off, SERDES channel analysis and PCB stack-up calculation etc.
• Proficient with 2-D/3-D CAD tools such as SIwave, PowerDC, HFSS, Hspice and Keysight ADS etc.
• Good working knowledge in various electronics test and measurement instruments like network analyzer, and oscilloscope etc.
• Familiar with DDR 3/4/5, PCIe Gen3/4/5, SAS/SATA, and USB, standard SerDes etc. Signal integrity simulation and analysis
• Good English in Read/Write
• Understand SI design flow and know how to co-work well with other function teams

Preferred Knowledge

• Experience of working in medium sized multidisciplinary development teams
• Ever work with Tier one customer like Google, Meta, Dell, HP etc.
• Fluent English in speaking/listening

1. Online interview with HM and peers.
2. Onsite interview with EE & Layout Managers.