1. High Speed IO digital design development.
2. Verilog RTL design implementation, function simulation.
3. FPGA synthesis and verification.
4. Design and project related document creation.

工作經歷：2年以上
學歷要求：碩士以上
科系要求：電機電子工程相關、資訊工程相關
其他條件：
Job Requirements:
1. 電機電子工程相關, 資訊工程相關
2. Familiar with Verilog RTL design
3. Familiar with FPGA emulation
4. Familiar with digital IC design Flow.
5. Ability to analyze and solve the engineering issues.

Skills in any of the following is a plus: