RAN4 Delegate

1. Delegate for Mediatek in RAN4. 2. Lead the RAN4 activities within Mediatek. 3. Participate the RF system development with RF system team.
Updated about 1 month ago
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RF System Architect Designer

1. RFIC architecture and specification design. 2. RF related calibration algorithm and control flow development/verification.
3
50K ~ 200K TWD/month
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RF System Engineer

1. RF IC circuit block verification and debug. 2. RF sub system verification and debug. 3. RF EVB design 4. RF ATE development. 5. RF calibration algorithm verification. 6. MP/FT support. 7. RMA su...
3
50K ~ 200K TWD/month
Updated about 1 month ago
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Analog Baseband Design Engineer

Responsible for analog baseband circuit design in wireless transceiver RFIC. Analog opamp, filter and TIA design Foundation analog IP design, including Capless LDO, bandgap, temperature sensor. Mix...
Updated about 1 month ago
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RF Circuit Design Engineer(PLL/XO)

1. RF IC design and verification. 2. Frequency synthesizer, phase-locked loop, VCO design.
3
50K ~ 200K TWD/month
Updated about 1 month ago
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RF IC design engineer

The candidate will design, supervise layout, help characterize transceiver front-end circuits for cellular, WiFi and bluetooth product.
3
50K ~ 200K TWD/month
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RF System Algorithm Architect

Advanced algorithm development for RF signal processing. Radio system modeling and analysis.
Updated about 1 month ago
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RF System Validation Engineer

1. RF IC circuit block verification and debug. 2. RF sub system verification and debug. 3. RF EVB design 4. RF ATE development. 5. RF calibration algorithm verification. 6. MP/FT support. 7. RMA su...
3
50K ~ 200K TWD/month
Updated about 1 month ago
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RFE Designer

Direct report to the RFE deputy director of technology PA designer or RFFE Module designer Build from scratch Short term KPI: Successfully to design proprietary in house RFFEM for the best benefit ...
Updated about 1 month ago
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RAN4/802.11 RF System Engineer

1. Delegate for Mediatek in RAN4. 2. Lead the RAN4 activities within Mediatek. 3. Participate the RF system development with RF system team.
Updated about 1 month ago
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RFFE Architect

RFFE engagement with 3rd party to identify Adv. RFFE technologies— including cellular and WiFi
Updated about 1 month ago
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RF Design Verification engineer

Take care of transceiver high level analog/digital/SW co-simulation Build Verilog model to do co-simulation with best efficiency
3
50K ~ 200K TWD/month
Updated about 1 month ago
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MMW IC Design Engineer / Senior Engineer

1. LNA, PA, mixer, IF buffer, LO chain design for >20GHz applications. 2. mmWave TX/RX IC subsystem integration, chip verification, and debugging.
Updated about 1 month ago
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Advanced Process Technology Device Analysis Engineer/Technical Manager

Advanced node device performance enhancement SI characterization and S2S improvement Yield sweet spot setting and device spot model targeting
Updated about 1 month ago
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Advanced Process Technology PPA Optimization Engineer/Technical Manager

DFM rule creation based on layout environment for process weakness DTCO for PPA enhancement Testline creation for process and device monitor
Updated about 1 month ago
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Senior ESD Design Engineer

ESD protection design covering fields for ESD/LUP design and simulation Whole chip ESD review and sign-off EOS/Surge/System ESD design experience is an added plus Work with project leader(analog/RF...
3
50K ~ 200K TWD/month
Updated about 1 month ago
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Senior Digital IC Engineer

Digital circuit design for DTCO(Design technology Co-Optimization)
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IR Signoff Analysis Engineer/Technical Manager

Develop the IR signoff criterion for leading process node and 3DIC. Maintain the IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable IR violation Develop n...
Updated about 1 month ago
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Timing Signoff Analysis Engineer/Technical Manager

Develop the Timing signoff criterion for leading process node and 3DIC. Maintain the Timing signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing violati...
Updated about 1 month ago
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Timing/IR Signoff Analysis Engineer/Technical Manager

Develop the Timing/IR signoff criterion for leading process node and 3DIC. Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/I...
Updated about 1 month ago
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SoC/3DIC on-die PI Optimization/Simulation Engineer/Technical Manager

Develop robust 3DIC PDN considering PDN impacts Build and analyze 3DIC IR results and propose solutions Define area-efficient stacking possibilities, robust PG structure for different IP styles Pro...
3
50K ~ 200K TWD/month
Updated about 1 month ago
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Physical-Design Methodology Engineer/Technical Manager

Co-work w/ foundry/EDA vendors to define best PD imp recipes Explore EDA tool new features and introduce to project team Define proper FOM to project DTCO opportunities Optimize PG structure for be...
Updated about 1 month ago
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Power Integrity Optimization Engineer/Technical Manager

Explore timing degrade considering power integrity for proper signoff criterion Explore EDA tool new features and introduce to project team Define area-efficient stacking possibilities, robust PG s...
Updated about 1 month ago
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Data Analysis & Machine Learning Engineer for Advance Process Nodes

Co-work with IT to build data stream of IC test result seamlessly Analyze data per knowledge about IC design flow, semiconductor devices, yield ramp up Communicate & collaborate with different in-h...
Updated about 1 month ago
50+
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DFT/MBIST Engineer for Advanced Process Node & Package Technology

DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: Scan chain insertion & ATPG pattern generation Pattern validation through simulation & silicon ...
Updated about 1 month ago
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ASIC Implementation Engineer

Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with...
Updated about 1 month ago
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SoC Design Technical Manager/Engineer

This position will be involved in the design methodology development with Foundry and EDA in leading-edge process node: Will work extensively with micro-architects to make best-in-class performance...
Updated about 1 month ago
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實驗室量測助理工程師

晶圓機台 & TLP/VFTLP 設定操作 高壓元件 SOA 測試與分析結果判讀 ESD 靜電防護測試與分析結果判讀
Updated about 1 month ago
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Spice Modeling Senior Engineer/Tech manager

An experience engineer with background on device characterization and spice modeling for advanced process nodes. Job responsibility: Qualify spice model and track S2S from Foundry Perform a wide ra...
Updated about 1 month ago
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Physical Design RC Extraction Engineer/Technical Manager

1. Physical design RC extraction flow development and build up. 2. EDA collaboration to enhance RC extraction methodology 3. FOM RC analysis to propose DTCO opportunities
Updated about 1 month ago
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