• Explore timing degrade considering power integrity for proper signoff criterion
• Explore EDA tool new features and introduce to project team
• Define area-efficient stacking possibilities, robust PG structure for different IP styles
• Provide quick assessment to IR severity and improved approaches

Qualification:

• 3+ year experience with IR-drop simulations, optimization and correlation
• Experienced with board development, signal/power Integrity
• Understand transmission line and electromagnetic theory
• Experienced with high speed digital interconnect design
• Experienced in fixing IR/EM violations w/ physical optimization
  
  

Preferred qualification:

• Experience with power integrity measurements as well as frequency/time domain
• Proficient scripting skill for data collection and analysis (Python, Shell)
• Experienced in optimizing PG grid structures considering tradeoff between metal layers and electrical spec