1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:
   1. Scan chain insertion & ATPG pattern generation
   2. Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
   3. Diagnosis to help manufacture process improvement
      
      
2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:
   1. PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
   2. Develop & integrate DFT-related RTL design modules to test chip

1. Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
2. Fluency in script language including but not limited to TCL/Perl/Python
3. Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
4. Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus