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ASIC Implementation Engineer

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Updated 28 days ago

Job Description

  • Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power.
  • Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
  • Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
  • DFT insertion, ATPG and gate-level simulation
  • Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
  • Interact with Physical Design Engineers and provide them with timing/congestion feedback.

Requirements

  • B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering
  • Experience with RTL Synthesis and design optimization for Power, Performance, Area
  • Knowledge of front-end related ASIC tools
  • Experience with EDA tools and scripting languages (Perl, Tcl) used to build tools and flows for complex environments
  • Experience with communicating across functional internal teams and vendors
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3
4 years of experience required
50K ~ 200K TWD / month
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