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ASIC Implementation Engineer
Job updated 12 mois ago
Description du Travail
- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power.
- Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
- DFT insertion, ATPG and gate-level simulation
- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
- Interact with Physical Design Engineers and provide them with timing/congestion feedback.
Profil demandé
- B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering
- Experience with RTL Synthesis and design optimization for Power, Performance, Area
- Knowledge of front-end related ASIC tools
- Experience with EDA tools and scripting languages (Perl, Tcl) used to build tools and flows for complex environments
- Experience with communicating across functional internal teams and vendors
50,000 ~ 200,000 TWD / mois
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À propos de nous
聯發科技成立於1997年，透過持續投資先進製程與前瞻技術，現已成長為全球領先的IC設計公司，提供涵蓋智慧手持裝置、智慧家庭應用、無線連結技術及物聯網產品等多個領域的系統晶片整合解决方案(SoC)，並居市場領先地位。聯發科技一年約出貨15億顆晶片落實在上億台的終端產品在全球各地上市。聯發科技提供高度整合與創新性的晶片設計方案，不僅協助製造商優化供應鏈及縮短新產品開發時間，還利於其在全球成熟及發展中市場建立競爭優勢。
聯發科技致力讓科技產品更普及，因為我們相信科技能夠改善人類的生活、與世界連結，每個人都有潛力利用科技創造無限可能（Everyday Genius）。了解更多訊息，請瀏覽：www.mediatek.com.
Équipe
Offres d'emploi
Temps plein
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Ancienneté moyenne à supérieur
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1
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35K ~ 200K TWD / mois
Temps plein
・
Ancienneté moyenne à supérieur
・
1
・
35K ~ 200K TWD / mois
Temps plein
・
Ancienneté moyenne à supérieur
・
1
・
35K ~ 200K TWD / mois