1. Using Verilog or SystemVerilog language to create behavior model of analog macro.
2. Integrating analog behavior model and digital block to run simulation to verify the function of mixed-signal system.
3. Digital verification flow development and maintenance

Familiar with Verilog/SystemVerilog language
Familiar with IC Design and Verification tools (VCS, Verdi, XUS, Virtuoso Composer)

Familiar with UVM/CRV is plus
Familiar with Power IC Design is plus
Familiar with Digital Design Flow is plus
Familiar with Synopsys/Cadence AMS platform is plus
Familiar with Perl/TCL/C++ is plus