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Timing Signoff Analysis Engineer/Technical Manager
11か月前に更新
職務内容
- Develop the Timing signoff criterion for leading process node and 3DIC.
- Maintain the Timing signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing violation
- Develop new Timing signoff methodology to be applied during chip synthesis/APR/STA.
- SPICE correlation for new timing signoff criterion
- Regression test for every signoff methodology by STA violation/slack analysis.
- Post-silicon data analysis for silicon-proven timing signoff criterion
職務要件
- "Knowledge of timing sign-off fundamentals : signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc. Experience using timing sign-off tools : PrimeTime/Tempus/HSPICE. Experience in design margin modeling, including CCS/AOCV/POCV/LVF is a plus"
- Understanding of programming fundamentals and concepts. Proficient programming skills in Python, TCL, Perl.
- Ability to collaborate effectively with different teams . Good communication to describe issues accurately to management.
- Familiar with timing sign-off factors : OCV/IR/thermal/Reliability , and spice simulation. Experience in on-die sensor design is a plus
- Experience in exploring and defining new process node sign-off criterion : N7/N5/N3/3DIC is a plus
- Familiarity with gate level design flows, such as PGB , place-and-route, schematic/layout design, RC extraction, physical verification is a plus
私たちについて
聯發科技成立於1997年，透過持續投資先進製程與前瞻技術，現已成長為全球領先的IC設計公司，提供涵蓋智慧手持裝置、智慧家庭應用、無線連結技術及物聯網產品等多個領域的系統晶片整合解决方案(SoC)，並居市場領先地位。聯發科技一年約出貨15億顆晶片落實在上億台的終端產品在全球各地上市。聯發科技提供高度整合與創新性的晶片設計方案，不僅協助製造商優化供應鏈及縮短新產品開發時間，還利於其在全球成熟及發展中市場建立競爭優勢。
聯發科技致力讓科技產品更普及，因為我們相信科技能夠改善人類的生活、與世界連結，每個人都有潛力利用科技創造無限可能（Everyday Genius）。了解更多訊息，請瀏覽：www.mediatek.com.
求人
フルタイム
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中級レベル
・
1
・
35K ~ 200K TWD / 月
フルタイム
・
中級レベル
・
1
・
35K ~ 200K TWD / 月
フルタイム
・
中級レベル
・
1
・
35K ~ 200K TWD / 月