【工作內容】
1. RTL to Netlist 設計流程規劃與實作 (RTL/Synthesis/STA/LEC)
2. New IP test-chip 開發/整合/驗證 , including pre-sim/post-sim.
3. standard-cell PPA分析

【必要條件】
1. Familiar with front end implementation design flow.
2. Familiar with digital simulation flow (e.g. ncverilog or VCS)
3. Familiar with synthesis tools.
4. Familiar with Verilog.
5. Proficient in perl or tcl or shell