Software Engineer for Vector/DSP library (Audio and AI)

2020-07-20Tech » Other

Job Description

The compensation package is negotiable and open to discussion during the interviews with SiFive. However, the salary is confidential information at SiFive. 40K+/month is shown here to be in compliance with the law in Taiwan and regulations of CakaResume.

RISC-V is a groundbreaking CPU instruction set architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively run by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.

As new RISC-V ISA extensions are prototyped, implemented, and standardized, SiFive will remain at the forefront of RISC-V innovation by shipping the highest performance, the lowest power RISC-V processors in the world. In order to achieve this goal, we need specialists in vector extensions. In the SiFive Vector team, you will build the RISC-V vector backend in LLVM (open source) and an AI-specific high-performance library.

The Challenge:

- Compute library optimization

- Co-work with HW members for architecture exploring and tuning

- Deep learning application/middleware integration

- Open-source software development/integration


What you bring to the challenge

- Familiar with C/C++11

- Experience with software performance tuning

- Basic understanding of Deep learning

- Basic understanding of Computer architecture

- Strong interpersonal skills and excellent team collaboration

40K+ TWD/month
Optional Remote Work

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About us

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information,


Grace Chen

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