The compensation package is negotiable and open to discussion during the interviews with SiFive. However, the salary is confidential information at SiFive. 40K+/month is shown here to be in compliance with the law in Taiwan and regulations of CakaResume.
RISC-V is a groundbreaking CPU instruction set architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively run by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.
As new RISC-V ISA extensions are prototyped, implemented, and standardized, SiFive will remain at the forefront of RISC-V innovation by shipping the highest performance, the lowest power RISC-V processors in the world. In order to achieve this goal, we need specialists in advanced compiler technologies who are passionate about extract the most performance possible from applications on advanced micro-architectures.
- Develop compiler and related toolchain for RISC-V processors
- Aid the RISC-V LLVM porting effort, and ensure that LLVM performs well on SiFive's platforms
- Define and implement advanced ISA extensions in LLVM and/or GCC
- Contribute to the RISC-V standardization process for advanced ISA extensions
- Participate in design discussions, planning, code review, documentation, open source processes, and other standard software practice.
- Follow the agile way of software development; effectively manage your individual project priorities, deadlines and deliverables.
What you bring to the challenge:
- 3+ years of compiler engineering experience
- Experience with LLVM/GCC development
- Experience with version control tool GIT, and development flow with GitHub, GitLab or Jenkins
- Experience with Auto Vectorization optimization or Vector/SIMD application development
- Knowledge of RISC ISA design and its optimization
The work environment is especially great if you are creative. We love working in a culture of growth and advancement.
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.