Verification Engineer

2020-07-20Tech » Other

Job Description

The compensation package is negotiable and open to discussion during the interviews with SiFive. However, the salary is confidential information at SiFive. 40K+/month is shown here to be in compliance with the law in Taiwan and regulations of CakaResume.

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs. As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive's rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

As a Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.

This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works. What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of the supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.


The Challenge

  • Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis
  • Develop checkers and assertions to verify the design.
  • Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans.
  • Write functional coverage, analyze both code and functional coverage, and close coverage holes.

Requirements

What you bring to challenge

  • A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.)
  • Familiarity with and/or ability to learn languages and methodologies that are not part of the industry-standard approach to verification (Scala, Chisel, etc.)
  • A conscientious and thorough approach to Design Verification
  • Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same
  • A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
  • Experience with prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms will be a plus
  • Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
1
40K+ TWD/month
Optional Remote Work

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SiFive

新竹市關新路27號5樓之5

About us

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.

Team

Grace Chen

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