陳嘉豪

新竹縣竹北市

+886 0989-929-413

工作經歷

一月 2017 - Present (5年)

碩士學歷

一月 2016 - 十二月 2016 (1年)

負責產品：SI(Silicon interposer)
工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作

指導教授：侯拓宏, 周正堂教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaO_x / TiO₂ bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程

2012 - 2014

Excel PowerPoint Word

6 years' experience in semiconductor field
Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
In charge of the product BCD with maximum output in the whole factory
Successfully improved more than 40 cases
Finished 2 of our company's top projects
Defined more than 60 best known methods(BKM)
Specialize in operating numerous equipment

Hsinchu, Taiwan

+886 0989-929-413

Jan., 2017 - Present (5 Years)

Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
Product：BCD(With maximum output), Logic
Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
  - HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
  - Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors

Jan., 2016 - Dec., 2016 (1 Year)

Product：SI(Silicon interposer)
Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica

Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaO_x / TiO₂ bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)　
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow

2012 - 2014

Excel PowerPoint Word