CakeResume Job Search

Advanced filters
Off
Logo of CakeResume Headhunting Recruitment Service.
• Ensure complete device integration, including analogue, digital IPs, memories, IOs and passives as required; • Conduct full IC specification to Final Netlist activities, including ownership for the validation/characterization upon silicon arrival; • Define the implementation and simulation strategies for optimal Mixed Signal IC execution (Design and Integration); • Design from initial written specification or ‘C’ model to final DFT inserted gate level RTL creation, Synthesis, insertion of Test
DFT
Synthesis
SystemVerilog
300台灣新竹市
3.5M ~ 5M TWD / month
10 years of experience required
Managing 5-10 staff
Logo of Google Taiwan.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in Multimedia or Low Power. Experience with ASIC low power flows and power management concepts. Preferred qualifications: Master's degree or PhD in Electronics Engineering or Computer Engineering/Science, with an emphasis on computer architecture, performance, and power analysis. Experience with power for multimedia IPs in mobile SoCs (e.g., ISP, codecs, d
CakeResume 2023 Career Fair
220台灣新北市板橋區縣民大道二段7號
Regular earnings reach NT$40,000
Logo of CakeResume Headhunting Recruitment Service.
• Defining the architecture and micro-architecture of WiGig/802.11ad MAC digital subsystems • SoC development and integration • RTL design using Verilog/System Verilog • Testbench and test cases development • ASIC emulation on an FPGA platform • Collaborating with the software and physical design teams to resolve any issues during the development process • Paying attention to design and implementation details, and documentation
ASIC
Digital IC
Verilog
Hsinchu, Hsinchu City, Taiwan
2.5M ~ 4M TWD / year
5 years of experience required
No management responsibility
Logo of Tensorcom.
Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra-low power, wireless communication chipsets, is looking for a candidate who is interested in working on complex, low power, ASIC designs for our next generation WiGig/IEEE 802.11ad compliant SoCs. The interested candidate will participate in a range of ASIC development activities such as defining the SoC architecture, the development of RTL code, the taping-out of the chip, and the evaluation of
40K+ TWD / month
2 years of experience required
No management responsibility
Logo of Panasonic Taiwan 台灣松下電器股份有限公司.
主要從事系統設計工作 1.網路通訊、廣播系統、網路錄影、LCD 顯示系統...等系統設計,公司另提供完善技能養成。 2.負責前述商材,進行通訊整合, 功能整合, 數據交換,提供客戶解決方案。 3.
VoIP
ASIC
USB技術
100台灣台北市中正區
42K+ TWD / month
1 years of experience required
No management responsibility
Logo of Ali Tech.
1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…
C++
FPGA
ASIC
台灣台北
台灣新竹市新竹
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
Co-work with ASIC design team for any architecture discussion, trouble shooting, and performance enhancement Create and maintain ASIC verification test code, SoC bring up System power consumption analysis and design Design and maintain API interface in SDK Occasionally schematic review for PCB design Develop turnkey solution by customer request
Embedded
RTOS
C
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of Altek 華晶科技.
1. ASIC影像演算法開發 2. 具AI/Deep Learning/Machine Learning相關演算法開發經驗者尤佳
AI
Python
C/C++
新竹科學園區
60K+ TWD / month
Logo of Conbiz Consulting Firm康彼斯顧問股份有限公司.
Role and Responsibilities: With the approaching and widely spread of WIFI technology, we are actively seeking talented engineer who will be responsible for system design, validation and optimization in hardware/system team. As a member of WIFI Hardware System team, you will participate in Wi-Fi system design, development, validation, integration and performance optimization. The responsibilities cover overall chip lifecycle development, including FPGA emulation, pre-silicon verification, ASIC br
300台灣新竹市東區
75K ~ 160K TWD / month
1 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
勢的5G通訊設備 🚩 薪資優渥 工作職責 - Experience with SPI, I2C interface development. - Experience with RF Crest Factor Reduction (CFR), Digital Pre-Distortion (DPD) and Closed-Loop Gain Control (CLGC) development. - Experience with RF calibration development. - Experience with RF test equipment measurements for power or spectrum or waveform quality in NR5G cellular standard. - Interface with cross-functional teams within the overall modem organization: ASIC design, modem/
C
C++
Taipei, Taiwan
1.3M ~ 2M TWD / year
5 years of experience required
No management responsibility

CakeResume Job Search

Join CakeResume now! Search tens of thousands of job listings to find your perfect job.