1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
No management responsibility