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Logo of MediaTek 聯發科技.
開發針對本公司晶片設計所使用的 EDA 工具,工作內容包含:需求分析,演算法設計,資料處裡,與使用者介面設計 推廣與嵌入新的流程到未來開案的晶片,目標是提升晶片開發的效率與品質 透過設
C/C++
Python
Perl
50K ~ 200K TWD / month
No management responsibility
Logo of 晶豪科技 ESMT.
1.維護Calibre SVRF rule file (Calibre LVS/ DRC/ XRC). 2.控管EDA License (Linux system/ Shell scripts). 3.維護與開發EDA自動化流程 (TCL/ Perl/ Python Language). 4.熟悉Synopsys, Cadence, SIEMENS EDA 軟體之使用.
60K ~ 200K TWD / month
2 years of experience required
No management responsibility
Logo of 菲博網獵聘股份有限公司.
1. 執行IOS平臺產品上架、開發與維護 2. 執行項目計劃,獨立完成編碼,完成開發任務 3. 執行產品功能,性能、質量負責,編寫相應模塊的設計、開發文檔 4. 提供積極創新,及時解決研發過程中發現的各類問題,運用相關技術手段不斷提升效率 5. 根據專案需求設計規劃iOS APP系統架構及功能模組 6. 協助部門領導,持續的優化相關產品的質量、性能及用戶體驗
Objective-C
Swift
iOS SDK
4.5M+ CNY / year
3 years of experience required
No management responsibility
Logo of 菲博網獵聘股份有限公司.
1.能按照產品需求獨立完成產品UI設計(web/mobile) 2.能獨立完成線上活動專題設計(web/mobile) 3.能獨立完成平面相關設計(平面物料和UI周邊設計) 4.能協助團隊完成日常運營設計(在線廣告重點是banner設計和小活動等) 5.能緊跟項目團隊步伐,有較強的執行力,做好相關時間管理
Photoshop
AI
UI Design
300K ~ 400K CNY / year
3 years of experience required
No management responsibility
Logo of 菲博網獵聘股份有限公司.
1、理解專案的背景和目標,深入理解專案的邏輯 2、對專案開發目標進行技術選型和決策,給出具體技術方案 3、對專案實現給出評估和完整排期 4、開發實現產品,對新有業務提供技術支援
laravel framework
Symfony
phalcon
450K ~ 600K CNY / year
3 years of experience required
No management responsibility
Logo of Realtek 瑞昱半導體.
Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design
EDA
Unix
Linux
60K ~ 150K TWD / month
5 years of experience required
No management responsibility
Logo of MediaTek 聯發科技.
Explore timing degrade considering power integrity for proper signoff criterion Explore EDA tool new features and introduce to project team Define area-efficient stacking possibilities, robust PG structure for different IP styles Provide quick assessment to IR severity and improved approaches
EDA
IR-drop
EM
50K ~ 200K TWD / month
4 years of experience required
No management responsibility
Logo of MediaTek 聯發科技.
Working on advanced node design methodology, PD execution and sign-off Develop advance clock tree structure Able to handle complex APR with 500+ hardmacros Project analysis in early stage
EDA
APR
TCL
50K ~ 200K TWD / month
No management responsibility
Logo of MediaTek 聯發科技.
1. Physical design RC extraction flow development and build up. 2. EDA collaboration to enhance RC extraction methodology 3. FOM RC analysis to propose DTCO opportunities
RC
EDA
50K ~ 200K TWD / month
4 years of experience required
No management responsibility
Logo of MediaTek 聯發科技.
PCIe/USB/MIPI-CSI/Display Port related high speed interface digital PHY IC design
Verilog
PCIe
EDA
50K ~ 200K TWD / month
No management responsibility

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