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Logo of CakeResume Headhunting Recruitment Service.
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
200 ~ 500 TWD / hour
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
1. New Product CP/FT testing program development 2. Mass Production RMA analyzing, test pattern enhacement 3. CP probe card and FT load board out-sourcing manufacturing evaluation
Testing
Semiconductor
IC design
2M ~ 3.5M TWD / year
3 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
Developing products and enhancing yield through Foundry Effectively managing NPI issues across teams, ensuring timely coordination and leading the transition to mass production Producing well-organized characterization reports, meticulously analyzing data to identify strengths and weaknesses in mass production implementation Proficiently communicating with customers and vendors, adept at facilitating tasks across internal teams and external parties Conducting advanced process and vendor evaluati
Semiconductor
MP
NPI
2.5M ~ 4M TWD / year
10 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
參與SSD韌體專案開發,進行硬體控制器的設計和實現,以達到高性能和高可靠性的要求。 參與新功能的研發並進行性能評估,確保SSD韌體的不斷優化。 與HW Engineer 密切合作確保專案順利執行。
FTL
Firmware
SSD
2M ~ 3M TWD / year
2 years of experience required
No management responsibility
Logo of 宏正自動科技股份有限公司.
格及系統設計規劃。成為專業的數位 IC 研發工程師,與我們一同開創科技趨勢新局! 【工作內容】 As a IC Design Engineer, you will design, implement and verify products that use FPGAs and/or ASICs. 1. Participate in the micro architecture and design partition within the FPGAs and/or ASICs and implement design blocks using
40K ~ 80K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of Morgan Philips Group.
【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.
UVM
Verilog
Verification
Regular earnings reach NT$40,000
2 years of experience required
No management responsibility
Logo of NVIDIA.
We are now hiring for a Senior Mixed-signal Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
Verilog
Mixed-Signal
PLL
5 years of experience required
No management responsibility

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