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Logo of Google Taiwan.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Experience with microprocessor architecture. Experience with logic design. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. Experience with modern processor microarchitecture and related technologies
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
Taipei, Taiwan
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
114台灣台北市內湖區
780K ~ 2.34M TWD / year
No management responsibility
Logo of Morgan Philips Group.
Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.
300台灣新竹市
1M ~ 3M TWD / year
3 years of experience required
No management responsibility
Logo of Ali Tech.
1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…
C++
FPGA
ASIC
台灣台北
台灣新竹市新竹
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
台灣台北市
200 ~ 500 TWD / hour
No requirement for relevant working experience
No management responsibility
Logo of ASML Taiwan 台灣艾司摩爾.
Introduction to the job Be a FPGA firmware design engineer and join the world’s most advanced electron beam defect inspection equipment development. Responsible for e-Beam inspection sustaining system improvement project, customer special request, and issue investigation. Firmware design support for new system and tool development. Product quality, reliability, and manufacturability improvement. Role and responsibilities FPGA HDL firmware design and development. Integrate and simulate RTL code f
台灣台南市東區臺南
Regular earnings reach NT$40,000
No requirement for relevant working experience
No management responsibility
Logo of 晶密股份有限公司.
【工作內容】 1. Define RISC-V micro architecture and RTL implementation 2. RISC-V behavior modeling 3. RISC-V design emulation
台灣新竹市新竹
1M ~ 2M TWD / year
5 years of experience required
No management responsibility
Logo of Google Taiwan.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Experience verifying digital logic at RTL using SystemVerilog for ASICs. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Experience with object oriented programming. Preferred qualifications: Master's degree or PhD in Electrical Engineerin
220台灣新北市板橋區
Regular earnings reach NT$40,000

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