CakeResume Job Search

1. SSD前端 PCIE APHY / DPHY / MAC電路驗證。 2. SSD前端 SATA APHY / DPHY / MAC電路驗證。 3. NVMe protocol & SATA protocol開發。

1. Be the VOC for quality-related topics within the organization to improve overall automotive customer quality satisfaction. 2. Directs, manages and coordinates cross-functional groups to achieve automotive customer quality requirements (CSR, questionnaire, ppm agreement, customer satisfaction survey ...etc) in a timely manner. 3. Work closely with internal teams on the RMA 8D problem-solving process to prevent reoccurrence. 4. Accountable for automotive customer audit and action follow-up

工作經驗: 0年工作地點: 台北市中山區學歷要求: 碩士工作項目： 嵌入式多媒體軟體開發 1. 開發與移植多媒體軟體平台 2. 嵌入式系統架構移植 3. 分析及改善多媒體系統效能 應徵條件： 具

1.高速 PLL 與 Serdes 的類比電路開發工作 2.負責Serdes PHY與PCIe/SATA PHY的開發與維護工作

Maintain並開發 SD Card相關 IP design.

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts

1.DDR Digital PHY design. 2.DDR3/DDR4/LPDDR3/4 memory control數位電路設計。

Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow.

工作經驗: 0 年 學歷要求: 碩士 工作項目： ARM Architecture based Complex CPU Subsystem Platform Design & Integration, Add-on Features Enablement and IP Development SoC Architecture Exploration, Performance Projection and Bottleneck Analysis Benchmark/Power Characterization on Emulation Platform, Result Analysis and Optimization CPU Architecture/Micro-architecture Research Involvement of Post-silicon Bring-up and Debug 應徵條件： 碩士以上；電機、資工、電子相

工作經驗: 0年 學歷要求: 碩士 工作項目 High-Performance CPU & GPU Frontend Implementation Advanced CPU Technology Development: High-performance, Ultra-low Power, and PPA Optimization Processor Frontend Development Flow Enhancement & Automation 應徵條件： 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 熟悉 Verilog RTL Design、SoC Integration & Design Flow、Frontend EDA