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數位 IC 設計工程師
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250萬 ~ 350萬 TWD / 年
需具備 5 年以上工作經驗
不需負擔管理責任
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This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
200 ~ 500 TWD / 小時
不限年資
不需負擔管理責任
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面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
180萬 ~ 300萬 TWD / 年
需具備 1 年以上工作經驗
不需負擔管理責任
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工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
400萬 ~ 500萬 TWD / 年
需具備 6 年以上工作經驗
管理 1 ~ 5 人
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1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh
SystemC
RTL
SOC
300萬 ~ 400萬 TWD / 年
需具備 10 年以上工作經驗
不需負擔管理責任
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Verify digital designs of large SoCs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology. Understand the design and implementation, define the verification scope, develop the verification infrastructure. Write and execute test plan to verify a design in a timely manner.
Design Verification
UVM
SystemVerilog
200萬 ~ 300萬 TWD / 年
需具備 2 年以上工作經驗
不需負擔管理責任
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碩士以上;電機、電機與控制、電信、電子相關科系畢業為主 需具備5年以上相關工作經驗 熟悉C、Verilog及一般IC設計流程,有數位 IC設計經驗或FPGA使用經驗,或通訊網路電路設計開發經驗者為佳 具數
Ethernet Switch
Switch
IC design
200萬 ~ 300萬 TWD / 年
需具備 5 年以上工作經驗
不需負擔管理責任
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1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
150萬 ~ 250萬 TWD / 年
需具備 3 年以上工作經驗
不需負擔管理責任
Logo of 晶豪科技 ESMT.
1. 設計感測處理器晶片的數位電路: 1) FIR/IIR digital filter design and implementation. 2) 32bit MCU AHB/DMA/UART/I2C/SPI/Timer/RTC/WDT/PIT/GPIO design. 3) digital/analog integration and co-simulation . 4) MAC design and optimization. 5) sensor algorithm development. 2. 開發測試程式: 數位
6萬 ~ 20萬 TWD / 月
需具備 1 年以上工作經驗
不需負擔管理責任
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自動交
FPGA
Verilog
7.5萬 ~ 10萬 TWD / 月
不限年資
不需負擔管理責任

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