CakeResume Job Search

Advanced filters
Off
Analog IC Design
Full-time
Logo of Accurate愛客獵-1111高階獵才中心.
產業類別: 生化科技研發 職責要求 • 熟悉類比訊號分析及電路設計能力。 • 相關開發經驗在小信號低雜訊類比電子電路的設計、模擬、Circuit Layout、電路量測及驗證。 • 熟悉OPAMP, Filter, ADC/DAC,… 規格, 性能特性及應用。 • 有能
類比IC設計
IC Layout
電子工程
1.1M ~ 1.3M TWD / year
8 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路,例如:USB4、PCIe5、25G serdes
ADC/DAC/Serds/PLL/LDO/BG/DP/HDMI/USB
USB4、PCIe5、25G serdes
PLL
2.5M ~ 4.5M TWD / year
3 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
專長是Class D Amp IP設計的類比IC設計人員協助產品研發, 且相關設計/產品經驗有 10 年以上 。 工作內容: 1. 負責HV Class D Amp新產品的評估, 包含前期的面積評估, 製程比較, 2. 以及中期的Class D Amp IP
Analog Design
Analog IC
Class-D
3M ~ 5M TWD / year
6 years of experience required
No management responsibility
Logo of 多方科技股份有限公司.
工作職責 (Responsibilities): Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. Work with digital team on specification definition Create behavior model for analog/digital evaluation Compliance test for SerDes IP
Linus
2.5M ~ 4.5M TWD / year
1 years of experience required
No management responsibility
Logo of Alpha & Omega Semiconductor (Taiwan) Ltd. .
1) DCDC Power IC design 2) Over 3~5 years experience in design house. power management is a must. 3) Review colleague's projects and own projects.
2M ~ 3M TWD / year
No management responsibility
Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of 通嘉科技 Leadtrend.
【工作內容】 1. 負責類比電源IC之設計/模擬/驗證/除錯 2. 管控類比電源IC之設計/模擬/驗證/除錯..等流程,追蹤相關流程進度 3. 撰寫各設計流程之設計/除錯分析報告 *意
60K+ TWD / month
No management responsibility
Logo of NVIDIA.
We are now hiring for a Senior Mixed-signal Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
Verilog
Mixed-Signal
PLL
5 years of experience required
No management responsibility
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 類比電路開發設計與佈局優化(Bandgap, LDO, Charge Pump等類比電路) 2. 非揮發性記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 3. 消費性、物
40K+ TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 力智電子股份有限公司.
1. High speed SAR ADC design (>200Msps) 2. High resolution SAR ADC design (14/16-bit) 3. Pipiline ADC design
台元科技園區
55K ~ 80K TWD / month
No management responsibility

CakeResume Job Search

Join CakeResume now! Search tens of thousands of job listings to find your perfect job.