CakeResume Job Search

• 面板驅動IC 或 SoC 設計

1. New Product CP/FT testing program development 2. Mass Production RMA analyzing, test pattern enhacement 3. CP probe card and FT load board out-sourcing manufacturing evaluation

Developing products and enhancing yield through Foundry Effectively managing NPI issues across teams, ensuring timely coordination and leading the transition to mass production Producing well-organized characterization reports, meticulously analyzing data to identify strengths and weaknesses in mass production implementation Proficiently communicating with customers and vendors, adept at facilitating tasks across internal teams and external parties Conducting advanced process and vendor evaluati

參與SSD韌體專案開發，進行硬體控制器的設計和實現，以達到高性能和高可靠性的要求。 參與新功能的研發並進行性能評估，確保SSD韌體的不斷優化。 與HW Engineer 密切合作確保專案順利執行。

This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform

面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

1. Facilitate collaboration between foundries and teams in Japan or Taiwan. 2. Maintain seamless communication channels with foundries regarding CP/FT-related updates. 3. Track product yield performance across various technologies and provide reports to headquarters. 4. Collaborate with headquarters and foundries to identify strategies for improving product yield. 5. Troubleshoot issues during mass production and collaborate with headquarters and foundries to sustain yield levels. 6. Gather tech

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh