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Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with microprocessor architecture through coursework or industry experience. Experience in logic design through coursework or industry experience. Preferred qualifications: Master's degree in Electrical Engineering or Computer Science with 2 years of relevant experience, or PhD in E
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with CPU or AI accelerator
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with microprocessor archit
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of Foreign Professional Talent Recruitment in Taiwan.
Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.
UVM
RTL
台灣台北市
2M ~ 4M TWD / year
3 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.
UVM
Verilog
RTL
台灣台北市
2M ~ 4M TWD / year
3 years of experience required
No management responsibility
Logo of WASAI Technology.
* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform. * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform. *You will join a growing team of digital IC design engineering professionals and have a real opportunity to have your hardware solutions
C
C++
OpenCL
台灣台北市
80K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
台灣台北市
200 ~ 500 TWD / hour
No requirement for relevant working experience
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Please complete your application before Mar 31, 2024. Minimum qualifications: Currently pursuing a Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or related technical field. Academic coursework in computer architecture (e.g., core, cache, memory, etc.). Experience with C/C++ or RTL. Preferred qualifications: Experience on open market MCUs (e.g., Rpi2040, STM32) and experience on small OS
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
台灣台北市
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor’s degree in Electrical, Electronics, Computer Engineering, Computer Science, or equivalent practical experience. 10 years of experience with CPU engineering, CPU program management, or similar experience. Experience with modern processor micro-architecture and processor design flows, RTL, Design Simulation and Emulation, and Physical Design technologies. Preferred qualifications: Master’s or PhD degree in Electrical, Elec
220台灣新北市板橋區
Regular earnings reach NT$40,000

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