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WASAI Technology

Verilog/VHDL Design Senior Engineer

* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals.* Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform....

Updated 27 days agoMonthly TWD 40,000 ~ 150,000

Full-timeEntry level台北

WASAI Technology

【實習】Verilog/VHDL/FPGA Design 實習生

* Studying and developing RTL code using VHDL or Verilog to accelerator kernels for Big Data platforms  * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform...

Updated 27 days agoHourly TWD 140 ~ 300