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WASAI Technology

Verilog/VHDL Design Senior Engineer

* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals.* Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform....

6 天前更新月薪 TWD 40,000 ~ 150,000

全職中高階台北