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Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
台灣台北市
200 ~ 500 TWD / hour
No requirement for relevant working experience
No management responsibility
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
台灣台北市
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of Andes Technology 晶心科技.
1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc. 2. Build testbench, develop and maintain in-house VIP 3. Create rand constraint conditions, analysis coverage holes and fill them 4. Create function coverage points to make sure all functions are under test
Verilog
C
C++
台灣新竹市新竹
50K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 智微科技股份有限公司.
1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.
Verilog
台灣新竹市新竹
60K ~ 80K TWD / month
No management responsibility
Logo of 台灣電子設計自動化股份有限公司.
TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the
Verilog
SystemVerilog
C/C++
80K ~ 200K TWD / month
5 years of experience required
Managing 5-10 staff
Logo of CakeResume Headhunting Recruitment Service.
Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.
UVM
Verilog
RTL
台灣台北市
2M ~ 4M TWD / year
3 years of experience required
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自動交
FPGA
Verilog
100台灣台北市中正區
75K ~ 100K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of Morgan Philips Group.
【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.
UVM
Verilog
Verification
300台灣新竹市
台灣新竹縣
Regular earnings reach NT$40,000
2 years of experience required
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自
FPGA
Verilog
100台灣台北市中正區
100K ~ 150K TWD / month
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
300台灣新竹市東區
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility

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