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負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路,例如:USB4、PCIe5、25G serdes
ADC/DAC/Serds/PLL/LDO/BG/DP/HDMI/USB
USB4、PCIe5、25G serdes
PLL
300台灣新竹市
2.5M ~ 4.5M TWD / year
3 years of experience required
No management responsibility
Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
台灣台北
台灣新竹市新竹
1.8M ~ 2.3M TWD / year
No management responsibility
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Lead the design of NAND flash IO circuits, ensuring optimal performance and reliability. Demonstrate proficiency in basic analog circuit design concepts, including LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Collaborate in conducting fail sample analysis and contribute to IC measurements to identify and address potential issues. If you have experience in NAND flash IO circuit design, a strong foundation in analog circuit design, and skills in fail sample analysis and IC measurement, we
台灣
2M ~ 4M TWD / year
5 years of experience required
No management responsibility
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Lead the top-level integration of analog IPs, encompassing projects related to SSD, UFS, eMMC, SD, and more. Demonstrate a solid understanding of basic analog circuit design concepts, including but not limited to LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Assist in conducting fail sample analysis and perform IC measurements to contribute to the identification and resolution of issues. If you have a background in analog IP integration, possess a strong grasp of analog circuit design
300台灣新竹市
2M ~ 4M TWD / year
3 years of experience required
No management responsibility
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Google welcomes people with disabilities. Minimum qualifications: Master's degree in Electrical Engineering, or equivalent practical experience. 8 years of experience with development of silicon-based ICs and chips. Experience in managing IP vendors. Experience in interface and analog mixed signal IP. Preferred qualifications: Experience in cross-functional collaboration with domain experts from architecture, design, power. Knowledge of PCIe, USB, UFS, CSI DSI, LPDDR protocols. Knowledge of PLL,
220台灣新北市板橋區
Regular earnings reach NT$40,000
Logo of 昇佳電子股份有限公司.
1.類比IP設計(Bandgap,OPAMP,ADC,DAC,PLL,Charge Pumping等) 2.熟悉hspice,Co-Sim等simulation tools,具晶片整合經驗佳
302台灣新竹縣竹北市
4 ~ 20 TWD / month
1 years of experience required
No management responsibility

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