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* Design and develop RTL for Big Data platform.
* Defines and documents RTL changes required for emulation/FPGA.
* Tests and debugs the emulation/FPGA model and collaterals.
Full timeEntry level
Updated 24 days ago
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application.
* Studying an...
1. FPGA firmware design (VHDL/Verilog)
2. IP usage and integration .
3. High Speed interface development.
4. Digital circuit design an...
Updated 9 months ago
FPGA firmware design (VHDL/Verilog)
IP usage and integration .
High Speed interface development.
Digital circuit design and analyze.
Issue analysis and solution....
Full timeMid-Senior level
The Senior FPGA (Design) Engineer will work at the system architecture level in multiple areas of the system as an expert in one or more significant technology domains and will serv...
Updated 3 months ago
1111獵才顧問中心Executive Recruiting Consultancy Dept.
FPGA firmware design (VHDL/Verilog)IP usage and integration .High Speed interface development.Digital circuit design and analyze.Issue analysis and solution.IP Core algotronix provides...
Updated 2 months ago
* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform.
* Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA.
* Tests and debugs the emulation/FPGA...
* Design and develop CUDA/OpenCL/HLS algorithms for HPC platform.
* Defines and documents CUDA/OpenCL/HLS algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model a...
新代科技股份有限公司 Syntec Ltd.
Updated 5 months ago
1. 熟悉I2C, UART, SPI, GPIO, PWM, ethernet, HDMI…之應用2. 韌體模組化和應用程式開發3. 擅長C/C++、RTL code (Verilog HDL, VHDL) 等程式語言及測試除錯能力4. 了解 Xilinx FPGA / MPU / MCU 並撰寫相關程式5. 熟悉感測元件的整合應用
Updated 4 days ago
1.Verilog HDL 設計
2.AXI4, DDR, PCIe等高速介面整合應用
Updated a month ago
customersParticipate in analysis of the problems reported by customersMentor and guide the junior members for better delivery and the management of the products and customer engagementsQualificatio...
JEDEC specificationExposure to LPDDR3, LPDDR4, LPDDR5 protocols & related controller/PHY designs stands highly desirableExperience with Shmoo or Memory diagnostic toolSupport eMMC/NAD/UFS memory tu...
16nm/10nm/7nm design experience is a plus.Solid skill sets of Cadence/Synsopsys/Mentor EDA tools.Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verificati...
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