MH Yeh

Mixed-Signal Verfication Engineer (MediaTek, 2019.12 ~ now)

Graduated from National Chiao Tung University, with three digital IC tape-out experience.

Mixed-signal verification engineer at MediaTek is my first job.

My friends always describe me like this: sociable, outgoing, easygoing, self-motivated.

Have reading habit,  I often use my spare time to improve myself.

Contact Information: [email protected] / +886 910 - 233462

Summary of Skill

Analog circuit behavioral modeling

SerDes/RF IP Verfication

Power-Aware Verification

Cell-based design flow

Work-flow automation

Computer Architecture









Shell script


CAD Tool

VCS/VCSMX (Synopsys)

Verdi (Synopsys)

Xcelium (Cadence)

QuestaSim (Siemens)


2016 - 2019

National Chiao Tung University

Institute of Photonic System (Master)

2016 - 2019

National Changhua University of Education

Industrial Education (Bachelor, Major in Electrical)


Master Period

Master Thesis

Develop a commercial real-time optical blood pressure algorithm platform, understand the LED Driver, TIA, PGA, Filter and ADC of the front-end analog circuit, apply digital signals to process digital signals, and complete a commercial real-time optical blood pressure algorithm program.

Digital IC Implementation and Testing

With one UMC18 process and two TSMC18 process Cell-Based IC tape-out experience, familiar with digital IC design process(include Verilog HDL coding, logic synthesis, APR. After chip back and packaging, building stimulus with FPGA, test chip on PCB board and display the results on a seven-segment. Except FPGA measurements, also established a VCD file to perform ATE testing with chip.

Ralated Papers

MH Yeh, PCP Chao, RK Pandey,"A New On-Chip Real- Time Algorithm for Non-Invasive Culess Blood Pressure Estimation Using PPG Sensor", ASME ISPS2019-7475.

KNG Priyanka, PCP Chao, TY Tu, YH Kao, MH Yeh, "Estimating Blood Pressure via Artificial Neural Networks Based on Measured Photoplethysmography Waveforms", Microsystem Technologies. 

Job Description

MediaTek (Mixed-Signal Verification Enginner, 2019.12 ~ present)

1. Assist analog engineers to complete the Verilog behavioral-model of Serdes circuits (Channel pulse model, Filter, PLL, TX/RX circuit, CTLE, DFE..) to speed up the system-level verification flow.

2. As a bridge between analog and digital IC design engineers, assist analog engineers to formulate circuit specifications, and when issues occur in Verilog simulation, find out bugs and clarify the cause of the problem.

3. Solve the long-runtime problem of Verilog simulation, find the circuit that consumes the most resources, modify the circuit behavior, release the workstation resources and simulator license.

4. Assist Chip top to design Low Power Design, help IP to create UPF file, and perform Power-Aware simulatiom.

5. Use script to automate the workflow, reduce the waste of human resources and the chance of human error, and use the parser to organize the log and visualize the data.

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