R&D staff process integration engineer of 14 nm FinFET devices, team player and specialized in process flow design. Strong understanding of devices (FinFET, power MOSFET). Capable of executing new packages to enhance electrical performance and yield. Experienced in data extraction, analysis, and DOEs. Familiar with layout (GDS) , mask (JDV) systems, and a programmer of Fortran and python.
English
Chinese (Native)