P5uxzvgpdyry2bchrfzt

Jing Yi Lin

R&D staff process integration engineer of 14 nm FinFET devices, team player and specialized in process flow design. Strong understanding of devices (FinFET, power MOSFET). Capable of executing new packages to enhance electrical performance and yield. Experienced in data extraction, analysis, and DOEs. Familiar with layout (GDS) , mask (JDV) systems, and a programmer of Fortran and python.

[email protected]

Work Experience

UMC, United Microelectronics Company

Staff Process Integration Engineer, Jul. 2019 - Now

  • FinFET SRAM platform FEoL development and yield excellence

Senior Process Integration Engineer, Oct 2015 - Jun 2019

  • 14 nm FinFET platform circuit layout and process flow design
  • Defined UMC's first 14 nm product logic chip process corners with work function metal
  • 3D silicon channel strain analysis and mobility boost by S/D Epi. processes
  • High-k metal gate dimensions design for power consumption reduction
  • MOL interconnect robustness, 14 nm FinFET yield peak 100%

Company@2x

Education

NTU, National Taiwan University

Master of Chemical Engineering, 2013 - 2015 

  • Silicon sheet electric zone melting thermal and crystallization simulation by phase field model, with finite element method and adaptive mesh by Fortran.
  • Poster exhibition at CSSC-8 (international workshop on crystalline silicon for solar cells) in Bamberg, Germany

Vevwzcfz5xss4zidykay

NTHU, National Tsing Hua University

Bachelor of Chemistry and Chemical Engineering, 2009 - 2013

  • Interdisciplinary degree of chemical engineering and chemistry

Vevwzcfz5xss4zidykay

Skills


English

  • TOEFL 96
  • TOEIC 945

Chinese (Native)



Software/Programming

  • Microsoft suite
  • AutoCAD/Inventor
  • Fortran
  • Python


Other skills

  • MOSFET/FinFET
  • SPC
  • GDS
  • JDV