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Avatar of 宋少傑.
Avatar of 宋少傑.
Past
Seller @Sell MAP Ltd (Shopee)
2022 ~ 2024
主任工程師
Within one month
.Back End Engineer- Manufacture of 3DIC-TSV technology products to customers. Education Bachelor of Electrical Engineering, Da-yeh University, Taiwan 2004~2008 Skills 1.UMC ULK Team group leader 2 years, experienced various projects (Cost down) (Defect) (Equipment CIP) (Productivity) (Recipe optimization.) (Machine capacity optimization) and achieved excellent results. 2.Excellent organization, coordination, and integration ability to cooperate with R&D/ Factory affairs/Manufacturer vendor/Quality Assurance/Process Units. 3.Problem-solving and statistical analysis. 4.SPC / FDC / FMEA / 8D Report / PDCA
SPC
FDC
FMEA
Unemployed
Ready to interview
Full-time / Interested in working remotely
6-10 years
大葉大學 DaYeh University
電機工程學系
Avatar of the user.
Avatar of the user.
Past
Senior Product Application Engineer @Mi Equipment
2021 ~ 2023
Senior Engineer
Within one month
DOE
FMEA Risk Analysis
MES
Unemployed
Ready to interview
Full-time / Interested in working remotely
6-10 years
Chung Yuan Christian University
Physic
Avatar of 王亦翰.
Avatar of 王亦翰.
Past
資深應用工程師 @添鴻科技股份有限公司
2022 ~ 2024
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
王亦翰 (Eason Wang) Since the beginning of work in 2013/9 to present with 10.5 years experience as an engineer. Main expertise is yield improvement, process technology and new product evaluate, and also handle customer complaint investigation. In my current position at CLC company as Sr.Application engineer in Sales Division. Contact information: E-mail: [email protected] Mobile:CAREER SUMMARY With 7.5-years experiences as engineer in Semiconductor Industry, mainly focus on yield improvement, process technical, new product evaluation, and handle customer complaint investigation. Familiar
PR inspect (EUVR & KrF)
Tool recipe setup
Process yield improve
Unemployed
Ready to interview
Full-time / Interested in working remotely
6-10 years
國立雲林科技大學 National Yunlin University of Science and Technology
材料科技研究所
Avatar of 邱耀慶.
Avatar of 邱耀慶.
Past
製程工程師 @漢民科技股份有限公司
2020 ~ 2023
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
開發新製程,協調客戶與公司部門內機台設計並優化製程參數。 製程工程師 • 聯華電子股份有限公司 七月三月 2019 | Taipei, Taiwan 利用SPC進行產品良率調控、產線優化、機台RECIPE參數調整、產線cost down計畫、2nd source更換quat plan、線上hold lot處理與trouble shooting 學歷 國立台灣師範大
Word
PowerPoint
Microsoft Office
Unemployed
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立台灣師範大學
化學
Avatar of Sax Chen (陳祥麟).
Avatar of Sax Chen (陳祥麟).
Senior Supplier Technical Assist @Ford Motor Company
2009 ~ 2011
GET/PROJECT MANAGEMENT/PRODUCTION ENGINEER/PRODUCTION SUPERVISOR/QUALITY ANALYST
Within one month
Sax Chen (陳祥麟) As a seasoned Supplier Quality Engineering professional with over a decade of experience, I bring a wealth of knowledge in supplier relations, quality management, and global sourcing, predominantly in the automotive industry. My journey has honed my skills in enhancing supplier performance, ensuring the timely delivery of high-quality components, and implementing lean improvement initiatives. I am recognized for my rapid learning curve and ability to swiftly navigate complex systems and diverse product ranges. A prime example of this was during my early days at Ford, where my proactive approach and commitment
Word
ppap
8D problem sovling
Employed
Ready to interview
Full-time / Interested in working remotely
More than 15 years
National Taiwan University of Science and Technology
Engineering/Industrial Management
Avatar of 許舜翔.
Avatar of 許舜翔.
製程技術研發工程師 @矽品精密工業股份有限公司
2022 ~ Present
Process Engineer
Within two months
過程,並有問題的時候到現場難排解疑,平常守時的習慣也會讓我想辦法使生產流線跟得上交期,並與現場溝通安排合理時程,使得各專案暢通達標。 學歷國立中山大學 National Sun Yat-Sen University 海洋環境工程 技能 Word PowerPoint Excel SAP SPC chart FMEA 語言 English — 中階 Chinese — 母語或雙語
Word
PowerPoint
Excel
Employed
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立中山大學 National Sun Yat-Sen University
海洋環境工程
Avatar of Blair Yu.
Avatar of Blair Yu.
Director of Product Engineering @SV TCL
2017 ~ Present
管理職
Within one month
Blair Yu Director of Product Engineering at SV TCL Multi-site and Multi-culture communication and team work experience (countries includes Autria, China, Czech, German, Neitherland, Mexico, USA, Switzerland) Problem solving with solid logic thinking Large team (30+ team members) leading and management People and team development Risk assessment with mitigation plan Team coaching and motivation Specialties: SPC, Statistic Process Control Skill and knowledge FMEA analysis and action plan Hsinchu, Hsinchu City, [email protected] https://www.linkedin.com/in/bert-blair-yu-pmp-89334a20/ 工作經歷 一
PowerPoint
Excel
Microsoft Office
Employed
Ready to interview
Full-time / Not interested in working remotely
More than 15 years
NTOU (Unofficial)
Material Engineering
Avatar of the user.
Avatar of the user.
Past
Team leader of Production Engineer @艾司摩爾
2016 ~ 2023
資深工程師、技術主管、專案管理工程師、產品經理
Within three months
Microsoft Office
SolidWorks
Matlab/Simulink
Unemployed
Ready to interview
Full-time / Interested in working remotely
10-15 years
National Taiwan University
Mechanical Engineering
Avatar of the user.
Avatar of the user.
Sr. Inspection Process Engineer @Corning Incorporated
2018 ~ Present
Technical support engineer
Within two months
Inspection Process
Machine Learning
Python
Ready to interview
Full-time / Interested in working remotely
10-15 years
National Sun Yat-sen University
Computer Science, Data mining, Database modeling
Avatar of 森 楊.
Avatar of 森 楊.
QC Associate Manager @Merck Group 台灣默克集團
2024 ~ Present
Manager
Within one month
月十二月 2021 ◆ Reliability and Quality project management Apple magnetic watch band Air pod pro Max internal component Huawei GT1&GT2 watch band ◆ Support Reliability Project and Quality control plan (Apple /Huawei/OPPO....) ◆ Quality tool: GRR/MTD/SPC/Machine qualification/Tool qualification/FACA ◆ FA analysis ability (OMM/CMM/FTIR/SEM/EDS/TGA/Instron…) Assist Process Engineer • United BioPharma. 一月十二月 2018 ◆ Fermentation Process of Biopharmaceutical and GMP operations. ◆ Process scale
Reliability
Analysis
Process Improvement
Employed
Open to opportunities
Full-time / Interested in working remotely
4-6 years
National Taiwan University
Master of Biomedical Engineering

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Technical Skills
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Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
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More than one year
R&D process integration engineer
Logo of  UMC.
UMC
2014 ~ 2022
Tainan, 台灣
Professional Background
Current status
Unemployed
Job Search Progress
Not open to opportunities
Professions
Electronics Engineer, Process Engineer, I&C Engineer
Fields of Employment
Electronics / Telecommunications, Nanotechnology, Semiconductor
Work experience
10-15 years
Management
None
Skills
Excel
reliability
Process Integration
Yield Enhancement
Failure Analysis
Languages
English
Intermediate
Japanese
Beginner
Job search preferences
Positions
Semiconductor Engineer
Job types
Full-time
Locations
Tainan, Taiwan, Kaohsiung City, 台灣
Remote
Interested in working remotely
Freelance
No
Educations
School
National Yang Ming Chiao Tung University
Major
Electrical Engineering & IC design
Print

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary

Resume
Profile

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary