劉柏頡 6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado). Experienced in script languages, such as Makefile, TCL, Perl and Python. Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC. Experienced in building some automatic flows using Jenkins and Git. Supervisor Engineer 城市,[email protected] Skills Language SystemVerilog & Verilog C/C++ Python Makefile Perl TCL Tool Xilinx Vivado Synplify/ProtoCompiler Xcelium
統上。除此之外,亦負責開發網路閘道器(Router)自動化驗證軟體系統,以及WiFi RF性能估測軟體系統,此系統除台灣分公司使用之外,亦使用於以色列分公司。 學歷 逢甲大學 Feng Chia University 自動控制,程式設計技能 Communication C C++ C# CSS JavaScript HTML/CSS 語言 Chinese — 進階 English — 中階
Communication
C
C++
Unemployed
・
Ready to interview
Full-time / Interested in working remotely
More than 15 years
逢甲大學 Feng Chia University
・
自動控制, 程式設計
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