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Past
R&D process integration engineer @ UMC2014 ~ 2022
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Semiconductor Engineer
More than one year
謝宗殷 (Azure) R&D technical manager Tainan City, Taiwan Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University. As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience. Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement. Email : [email protected] Phone:Work experience R&D technical manager • UMC JuneMarchnm FiNFET BEoL process development, product yield improvement and
Unemployed
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Not open to opportunities
Full-time / Interested in working remotely
10-15 years
National Yang Ming Chiao Tung University
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Electrical Engineering & IC design
Past
製程工程師 @台灣積體電路公司2018 ~ 2020
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研發工程師
Within six months
setup 3. cost reduction 80w/month 4. slot effect improve 50% 5. defect improvement from 5 to 3 count/ wafer 台灣積體電路公司, 製程工程師process engineer, Jun 2018 ~ SepF18 N5 FEOL new tech transition 2. FINFET CD / depth SPC maintain 3. WPH improvement 50% 4.new tool import for production line expansion 5. DOE design uniformity improve 30% 6. Auto system coordinator and APC setup Equipment Process: TEL SCCM/VIGUS/F1000 Hitachi 9012 Measurement: (CDSEM/ SCD/
Unemployed
Full-time / Interested in working remotely
4-6 years
成功大學
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