Chun Ching Chan (Alan)
Analog Integrated Circuit (AIC) Design Engineer who has held in key positions in a variety of designs T-CON and RF circuits. Proficient in knowledge about high speed, I/O, power for IC designs.
Have 4 papers was publish by IEEE Journal & Conference.
Master's degree in Electrical engineering.
High speed interface IC design engineer/ RF IC design engineer
Hsinchu，TW 1990/08/24 (29 years old)
[email protected] / 0910-087-358
Core Qualifications
• Executed two projects into mass production.
• Experienced in whole chip floor plan.
• In-depth knowledge of VLS IC designing.
• Proficient in computer aided designing applications.
• Excellent analytical, problem solving and troubleshooting skills.
• Communicative with clients and colleagues
• Ability to work on multiple projects simultaneously
Working Experience
Raydium Semiconductor Corporation (Hsinchu)，June 2017 - Present
Position: Analog IC Designer
In charge of design below blocks & IPs in three projects:
• Buck convertor: Current mode 60mA η=88% @800kHz~2.4MHz. ZC. Cap Multiplier.
• PD: SSA, Demux. Saving power with 15%.
• LVDS: Input Resistor diff. EOS 10V, Freq. detect, VCM VID detect (fail safe mode).
• VCO: 2 stage, 4 stage ring 80MHz~4GHz.
• AUX: Driving current 20mA, EOS10V. • OSC: 54MHz temp. variation ±1.5%.
• LDO: 300uA, 3mA, 30mA. Leakage debug.
• Band-gap: start up, noise improve, operation voltage Low to 1.2V for 3.3 device.
• I/O design: GPIO, OPDIO, GPI, SDR, DDRII, EOS 10V. • PLL, DLL, POR, POC, ESD detect.
Designed buck convertor which could integrated with T-CON system.
Developed and improved EOS structure from 6V fail to 10V/1mA.
Communicated and co-work with several departments such: digital, APR, ESD,
Layout and SA to ensure that all the designs are made in compliance with the design and safety standards.
Education
National Central University (2013-2016)
Master's Degree in Electrical Engineering (GPA 4.0)
Tamkang university (2008-2013)
Bachelor degree in Electrical Engineering
Academic publication
Journals
1. “Design and Analysis of CMOS Low-Phase-Noise Low Quadrature Error V-Band Subharmonically Injection-Locked Quadrature FLL“ IEEE Trans. Microw. Theory Techn., 2018.
2. “Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique” IEEE Trans. Microw. Theory Techn., 2016.
Conference
1. “A V-band Low-phase-noise Low-jitter Sub-harmonically Injection-locked QVCO with High Quadrature Accuracy in 90-nm CMOS Process” IEEE MTT-S International Microwave Symposium, 2017.
2. “A 31.2% Locking Range K-band Divide-by-6 Injection-Locked Frequency Divider Using 90 nm CMOS Technology” IEEE MTT-S International Microwave Symposium, 2015.
Technical skills
• Simulation: Hspice, Finesim, Cadence, Spectre, AFS
• Schematic: Cadence, ADS, OrCAD, Simulink
• Layout: Laker, Cadence
• EM: Sonnet, HFSS
• Other: Maple, Origin
Reference:
Available Upon Request
