Avatar of Benjamin Wan.

Benjamin Wan

Digital IC Design Engineer
Digital Design Engineer, have been working in IC Design for more than 3 years. Apart from the hardware design work, I also spend my time studying deep learning and robotics.
Allystar Technology Co. Ltd
The University of Hong Kong
Hong Kong

Skills

C++
Verilog HDL
Python
Tensorflow (Keras)
Linux

Languages

Chinese
Native or Bilingual
English
Professional

Work experiences

Digital IC Design Engineer

Allystar Technology Co. Ltd

Mar 2018 ~ Present
-Worked for Baseband Technology Team of GPS SoC ASIC project -Designed Fast Fourier Transform accelerator -Used Python to design digital signal processing model for hardware design and testing -Used C to implement embedded software ROM code for baseband debug and performance test

Digital Design Engineer

Deepsky Corporation Limited

Jan 2017 ~ Dec 2017
1 yr 0 mos
-Worked for Digital Design Team and helped to build LED display controller -Designed 2D graphics controller for on-screen display -Designed hardware bootloader for embedded processor

FPGA Design Engineer

CTAccel Limited

Dec 2015 ~ Jul 2016
8 mos
-Supported the development and testing of company products -Setup testing environment on ZYNQ Zedboard to evaluate Xilinx Video IP -Created control module of Xilinx Video IP for the integration of the IP into image scaler accelerator product

Educations

The University of Hong Kong

Master of Science (MS)
Electrical & Electronic Engineering

2017 - 2020
Description
Study: -Machine Learning -Deep Learning -Data Mining -Computer Vision -Digital Signal Processing Coursework: -Brain MRI Segmentation using ResNet-V2 & Keras -CIFAR-10 challenge using Inception Network & Keras FYP: -Deep learning application in autonomous mobile robot

Imperial College London

Master of Science (MS)
Electrical & Electronic Engineering

2011 - 2015
Description
I studied 4 years covering the Bachelor and Master program FYP: -Work-stealing for ZYNQ FPGA Applied work-stealing principle to design multi-thread scheduler in C++ to offload CPU work to FPGA
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