Litho-EUV Process Engineering
TSMC_台灣積體電路製造股份有限公司(台積電)
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Full-timeExperience in middle-end for tech N5 / N4 and front-end for tech N3 process.
Daily production supports semiconductor processes related to Litho-EUV.
- Inline/offline statistical process control (SPC) monitoring.
- Wafer overlay/pattern performance analysis and improvement (troubleshooting and optimized process parameters).
- Inline defense system improving. (Residual Overlay Performance Indicator / Etching to Litho difference)
Co-work with process integration engineers to implement new processes/experiments to improve manufacturability and avoid low yield.