Hsieh Azure
R&D process integration engineer
Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device
reliability improvement.
Email : [email protected]
Phone: 0910-828-616
Skills
Languages
English
・
Intermediate
Japanese
・
Beginner
Work experiences
R&D process integration engineer
UMC・Full-time
Jun 2014 ~ Mar 2022
・
7 yrs 10 mosTainan City, Taiwan
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design
3. 22nm eHV (device operate in 8V-27V) interconnect process develop
Process integration engineer
Taiwan Semiconductor Manufacturing Company(TSMC)・Full-time
Jul 2010 ~ Apr 2014
・
3 yrs 10 mosTainan City, Taiwan
Process integration engineer in 40nm - 90nm mature technology
1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc)
2. 20nm process transfer from Hsinchu to Tainan
Educations
National Yang Ming Chiao Tung University
Master’s Degree・Electrical Engineering & IC design
2006 - 2009
Description
Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter
Chang Gung University，CGU
Bachelor’s Degree・Electrical Engineering Department
2002 - 2006
