洪仲 Reavic
HW Engineer
-3+ years experience in FPGA/CPLD development.
-3+ years experience in HW development.
-3+ years experience in BIOS/BMC FW test.
-Familiar with FPGA/CPLD development process/Verilog coding.
-Familiar with HW development process.
-Familiar with X86 Server product architecture.
-Looking for jobs: FPGA/CPLD Engineer/Digital IC Design Engineer/Hardware Engineer
Skills
Languages
English
・
Intermediate
Work experiences
HW Engineer
Universal Global Scientific Industrial Co., Ltd.・Full-time
Dec 2013 ~ Jun 2023
・
9 yrs 7 mosCaotun, Caotun Township, Nantou County, Taiwan 542
Work Experience：
Hardware Development：
-Schematic Design(Co-work with Power RD) and create BOM for RFQ.
-Placement and Layout/Gerber Out(Co-work with SI/MD/Layout RD and review BRD).
-HW DV、Debug & Re-work.
-Build HW part application process and keep management/optimization.
Finished board：
Server：
-PIB*4/Wireless Adapter of System(Icelake-D)--MP
-Power Switch Fixture for optimize MFG.--MP
-BP Switch Fixture for optimize MFG.--MP
-1U PCIE/M.2 Riser Card of System(Icelake-D)--RFQ
NAS：
-Mezzine Card(Marvell 88E1512)--RFQ
-Netgear Expansion Box(Marvell 88SM9705)--RFQ
-Netgear SATA Daughter Board(Marvell 88SE9485+88SM9602)--RFQ
-SATA HBA Card(Marvell 88SE9170)--RFQ
FPGA/CPLD Development：
-Build verilog code base on customer's spec.
-Build testbench for simulation.
-Code Programmer、Test/Verification、Debug.
Finished board：
-Virtual Device Fixture--DOC/In-house patent.
-NXP LS1046A SOC preliminary bring-up.
-Qualcomm QDF2400 MB bring-up.
BVT Test Team Management/Contact.
-Executed the BVT test of 6 Server products.
Educations
National Yunlin University of Science and Technology
Master’s Degree・Electronic and Optoelectronic Engineering(MS in Electronic Engineering)
2010 - 2013
Description
碩論：1~4G三軸加速度計與感測電路整合晶片
我們要實現一個跌倒偵測晶片，所以選用加速度計來達到要求
-加速度計元件組成：感測結構和讀取電路
-利用CMOS MEMS製程整合優點：
-去除整合上雜訊過大的問題
-可靠性
-可大量製造，設計商品化
Licenses & Certifications
電腦硬體裝修乙級
行政院勞工委員會
Issued May 2006
・
No expiration