YiHsuan Liang
: A dedicated and self-motivated engineer with 2+ years experience in FPGA and ASIC design, including RTL coding, synthesis, simulation and scripting automation. Hands-on experience in testbench development in UVM environment.
Taoyuan City, Taiwan 0975176232 [email protected]
Skills : UVM, Sysytemverilog, Verilog, VHDL, Perl, TCL, Matlab, C
EDA: Cadence Xcelium, Simvision, Xilinx Vivado, Intel Quartus, Lattice Diamond, Siemens Questa
Experience
Digital Design Engineer
Analog Device
Mar. 2023 - Present
- Verify slave subsysyem of AMBA Soc
- Create / Modify existed testcase to maximize coverage
- Develop UVM testbenches at block level simulation
- Maintain low power IP
FPGA Design Engineer
Wistron Neweb Corp.
Apr. 2021 - Feb. 2023
- Integrate FPGA designs into projects
- Develop simulation environment to verify FPGA designs in RTL
- Work with hardware design team to debug test failure
Education
University of Leeds
Master of Electrical and Electronic Engineering
Sep. 2019 - Sep. 2020
National Taiwan Normal University
Bachelor of Mectronic and Electronic Engineering
Sep. 2013 - Sep. 2017
Skills
‧Basic understanding of several protocols, including UART, I2C, SPI, LPC, I2S and USB.
‧Knowledge of VHDL/Verilog and UVM
‧Experience with AMBA SoC
Languages
‧Mandarin - Native
‧English - Advanced
‧Spanish - Beginner
