YiHsuan Liang

: A dedicated and self-motivated engineer with 1.5 years experience in FPGA design, including RTL coding, synthesis, simulation and scripting automation. I possess a genuine passion for improving my knowledge of test bench development, system-level simulation and UVM.

  Taoyuan City, Taiwan   0975176232    [email protected]

Skills : VHDL, Verlog, Sysytemverilog, Matlab, C

EDA: Xilinx Vivado, Intel Quartus, Lattice Diamond, Mentor ModelSim

Experience

FPGA Design Engineer

Wistron Neweb Corp.

Apr. 2021 - Present

- Integrate FPGA designs into projects

- Develop simulation environment to verify FPGA designs in RTL

- Work with hardware design team to debug test failure 

Equipment Engineer

Cyntec Co. Ltd.

Doc. 2018 - Aug. 2019

- Troubleshoot day-to-day process problem

- Monitor and maintain stability of production equipment

- Improve quality pass rate and decrease downtime

Education

University of Leeds

Master of Electrical and Electronic Engineering

Sep. 2019 - Sep. 2020

National Taiwan Normal University

Bachelor of Mectronic and Electronic Engineering

Sep. 2013 - Sep. 2017

Skills 

‧Basic understanding of several protocols, including UART, I2C, SPI and LPC 

‧Knowledge of VHDL/Verilog and coding skills for synthesizable FPGA designs

‧Experience with using different simulator

Languages

‧Mandarin - Native 

English - Advanced 

Spanish - Beginner

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