Responsibilities

• Writing clean, high-quality, high-performance, maintainable RTL code
• Participation in code reviews
• Implement Verilog RTL from a high-level description such as one in Matlab, Python or C.

Qualifications:

• Bachelor’s degree in EE or CS
• Familiar with RTL simulation, timing analysis.
• Familiar with FGPA digital validation and test pattern generation using logic analyzer and/or high-speed oscilloscope, etc.
• Familiar with Xilinx FPGA process in memory.
• Familiar with Xilinx IP design and packaging.
• Familiar with at least one FPGA device.
• Familiar with Custom IP and SoC integration is a plus.