We are looking for candidates with experiences in ASIC SOC front-end design and integration. In this position, you will build complex SOC chips, work closely with Architecture, RTL Design, Physical Design, CAD, Package Design, and other teams. Additionally, you will be involved in defining and building methodologies that create more efficient and flexible SOCs.

What you will be doing:

• Work with some of the best engineers to define architecture and execute plans at both IP and full chip level.
• Analyze design trade-offs and optimize design based on features, requirements, and system limitations.
• Front-end design, quality checks, and coordinate with the verification engineers to ensure that the design is functional.
• Develop flows and tools as vital in support of design activities.
• Support post-silicon validation activities.

What we need to see:

• Bachelors or Masters' Degree in EE, CS or CE or equivalent work experience.
• 3+ years of industry experience.
• Proficiency with Verilog, System Verilog, C/C++.
• Deep understanding of SOC architecture and design concepts.
• Outstanding analytical skills and problem-solving skills.
• Good written and verbal communication skills.

Ways to stand out from the crowd:

• Knowledge about features of complex SOC's including CPU, Memory, Interconnects, Clock/Reset, power management sub-systems.
• Knowledge of system level design concepts.
• Experience in building ASIC design flows.
• Experience working in a globally distributed team.
• Proven scripting experience (Python, Perl, TCL, shell programming)