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Hsinchu City, Taiwan
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NASDAQ Well Known High Speed IC Design- Design Verification Manager
CakeResume Headhunting Recruitment Service
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
1
・
・
Hsinchu City, Taiwan
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
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