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Mid-Senior level
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進行PCB的層層堆疊阻抗設計及SI/PI模擬分析。 撰寫版面設計指南並執行版面品質檢查。 審核並排除訊號量測問題
SIPI
signal&power integrity
Signal Integrity
1.2M ~ 2.8M TWD / year
2 years of experience required
No management responsibility

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